1. Field of the Invention
The present invention relates to an integrated circuit testing device for testing the functions and electrical properties of semiconductor integrated circuits.
The present application is based on Patent Application No. Hei 9-52059 filed in Japan, the content of which is incorporated herein by reference.
2. Conventional Art
FIG. 4 is a block diagram showing the structure of a conventional integrated circuit testing device. In this drawing, the pattern generator 1 is a device for sequentially generating input test patterns in time series and expected value patterns corresponding thereto.
The control circuit 2 is a means for selecting either the driver 3 or the comparator 4 for each pin in the device under test 5. That is, the integrated circuit testing device has multiple pairs of drivers 3 and comparators 4 (in order to prevent the drawing from becoming too confusing, FIG. 4 shows only the driver 3 and comparator 4 corresponding to a single pin), and each pin of the device under test 5 is connected to a pair. The control circuit 2 selects and connects a driver 3 to each pin which is an input terminal of the device under test 5, and selects and connects a comparator 4 to each pin which is an output terminal.
Under selection control due to this control circuit 2, the selected drivers 3 supply input test patterns generated by the pattern generator 1 as input signals to the pins (input terminals) of the device under test 5. Additionally, the selected comparators 4 form the output signals obtained from the pins (output terminals) of the device under test 5 into digital signals by comparing them with standard levels determined by a device test program.
A judgment circuit 6 compares the binary data obtained from the comparators 4, i.e. the binary time series pattern of the output signals from the device under test 5, with the above-mentioned expected value pattern, and judges whether or not the device under test 5 is functioning normally.
If, for example, the device under test 5 is a RAM, this integrated circuit testing device can perform function tests in the following manner. First, data A is generated by the pattern generator 1 as an input test pattern, and this data A is written into the device under test 5 through the drivers 3. Subsequently, an input test pattern for reading memory data from the device under test 5 and an expected value pattern which is identical to the above-mentioned data A are generated by the pattern generator 1. Then, the input pattern is introduced to the device under test 5 through the drivers 3, as a result of which the signals output from the device under test 5 (i.e. the memory data) are formed into a binary signal by the comparator 4 and sent to the judgment circuit 6, at which time it is compared with the data A which is generated as an expected value pattern. In this comparison, the memory operations of the device under test 5 are normal if the binary data received from the comparators 4 match the data A which is the expected value pattern, and if there is no match, then there is an abnormality in the memory operations of the device under test 5.
With the conventional integrated circuit testing devices as explained above, it is possible to perform logic function tests of various semiconductor integrated circuits if an input test pattern and an expected value pattern are prepared for each function of the device under test.
However, when performing tests of semiconductor integrated circuits, the expected value patterns are not necessarily always capable of being prepared, and at times judgments must be made of the devices under test without the expected value patterns.
For example, when the device under test is a memory element and the content of the memory is unknown, then a test must be performed on the unknown data stored in the device under test.
As one type of test for unknown data, there is a test for a case wherein the same unknown data are stored in a plurality of locations in a single device under test, wherein it is judged whether or not the unknown data are truly identical.
Additionally, as another type of test for unknown data, there is a test for a case wherein the same unknown data are stored in a plurality of devices under test (the unknown data stored in each of the devices under test can be either single or plural), wherein it is judged whether or not the unknown data are identical.
Since this type of conventional integrated circuit testing device cannot collate the unknown data when the device under test stores unknown data, it cannot perform such tests of unknown data.